1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and more particularly, to a duty cycle correction circuit.
2. Related Art
In general, double data rate synchronous dynamic random access memories (DDR SDRAMs) are configured to increase an operational speed by processing data using both a rising edge and a falling edge of a clock signal. However, if a duty ratio that is a ratio between a rising edge period and a falling edge period of the clock signal is not maintained at 50:50, operational efficiency is deteriorated. In actuality, a clock signal that is used in a semiconductor integrated circuit (IC) rarely has an accurate duty ratio due to various factors, such as noise within a mounting environment of the semiconductor IC. Thus, a semiconductor memory apparatus, such as the DDR SDRAM, includes a duty cycle correction device that corrects a duty ratio of a clock signal to improve operational efficiency.
A duty cycle correction circuit of a general semiconductor memory apparatus charges voltages during high-level and low-level periods of an input clock signal, compares levels of the charged voltages, and detects a duty ratio of the input clock signal. The semiconductor memory apparatus performs a control operation using the detection result, such that the high-level period and the low-level period of the input clock signal have the same length.
However, since a general duty cycle correction circuit continuously operates even when a high-level period and a low-level period of a clock signal are controlled to have the same length, current consumption is large. Thus, a duty cycle correction circuit having small current consumption has been required.